Information Flow and Timings

Instead of starting at the logic gate level and moving outward. It's best I believe to start as a general overview. Almost like writing a novel. You have to step back and figure out a very generalized sense of the flow of things before you delve into the details. I've already outlined several points in the last post that I want to be a requirement.
Now the next stage is figuring out how I would like the processor to process that information. Here comes the pipeline. One major decision I had to make was whether I wanted to make a linear or non-linear pipeline. One advantage of having a non-linear pipeline is that the processor can have variable length instruction sets: so there can be more flexibility and potential memory saving. This is great, but can be more complicated both to design and program on the machine language level. I have decided for simplicity sake to go with a linear pipeline to allow easier design and programming.
Another thing I had to think about was instruction set size. It seemed logical to me to make it in lengths that are multiples of 8-bits because this is an 8 bit machine. There are 4 things minimum a computer must know to fulfill an instruction. Think of language. One can make a sentence from 2 words. "James walk." This is a noun and a verb. In a general sense a computer manipulates data based on other data: so there must be 2 "nouns" and 1 "verb". Then once that data is finished processing it needs to be put somewhere, and the processor needs to know where. So that's 3 "nouns" and 1 "verb". So in the end we have 4 pieces of data.
[Instruction, Data 1, Data 2, Result location] 
Which in more technical terms is
[opcode, register/constant 1, register/constant 2, register for output]
Beautiful. In the end that is 4 instructions of length 8 bit. So therefore we have a 32-bit instruction set. This may be re-ordered later, and depending on how many opcodes/instructions will be laid out, there may be room to squeeze some bits for different memory bank locations there. But for now we'll put that to the side.

Moving on though: I remember the day when those synapses' connected and it suddenly clicked how the clocks work on a computer. This discovery came when I was trying to figure out how to make logic gates move from one operation to another and was really frustrated. Then I thought "I need some kind of signal that changes regularly to activate the circuit and allow things to settle before changing again. This was until all of a sudden in a single burst it came to me: That's what a computer clock does! Then I quickly drew a diagram like this.

When the signal from the clock goes high, it follows the top path and based on the line number determines the operation to be performed. Once it finishes it's operation, it updates the line number for when the clock goes high. The clock then goes high and the cycle continues but in vice versa.

One thing that limits a computer is bandwidth. I was really wanting to design this computer with the notion of using multi-port memory. (Memory that can be written/read by multiple channels). But alas, reality has finally settled in and I am forced to design to the constraints of available equipment. If multi-port memory was widely available: I could design the CPU to take a half clock pulse and in that time read from memory, manipulate the data, and output all in one shot. But again, that's not reality. This 8 bit processor must read 8 bits at a time and output 8 bits at a time.

I then had to come up with a realistic flow and update the diagram. I at first was thinking of a tree like structure that uses flags to follow a path based on the bytes coming in, but I realized that this would get complicated real fast. That structure is better suited for a variable length instruction set. I then got the brilliant idea to load the chunks in first, then perform the operation in one swoop with the loaded bytes stored in temporary registers.

Based on that flow, this is the updated diagram

Here it says load chunk: This is synonymous with loading the byte.

I'm excited to be at this point. From here I need to design an instruction set and the layout more specifically memory and get finer details laid out for the White Blaze architecture